The present invention is related to a memory for storing a data array, and is more specifically related to a programmable memory architecture, and a method of reorganization of stored data for enhanced memory performance.
Read only memories (ROMs) are used to store customized data in an array for retrieval in a user's application. Examples include operating systems in programmable devices such as computers, programs in game cartridges for game consoles, tables for table-look up in applications such as encoders and decoders, code conversion applications as performed by compilers, and other applications where some customized data that will not change with use of the application is needed for the operation of the application.
Referring to FIG. 1a, a ROM array 8 consists of a plurality of memory cells 10.sub.11 . . . 10.sub.44 arranged in rows 12.sub.1 . . . 12.sub.4 and columns 14.sub.1 . . .14.sub.4. Each memory cell in a column is coupled to a bit-line 16.sub.1 . . . 16.sub.4 consisting of a bit-line true and bit-line complement. The content of the memory cells is read through the bit-lines 16.sub.1 . . . 16.sub.4. Each memory cell in a row is coupled a word line 18.sub.1 . . . 18.sub.4 used to select the appropriate cell in memory to be read. ROM memory cells 10.sub.11 . . . 10.sub.44 are generally composed of a single n-channel or p-channel transistor. Typically, the data in the array is known when the ROM is being manufactured. The memory cells 10.sub.11 . . . 10.sub.44 contain a transistor connected to the bit-line 16.sub.1 . . . 16.sub.4 and word line 18.sub.1 . . . 18.sub.4 for the memory cell when the memory cell (e.g., 10.sub.21, 10.sub.22, 10.sub.23, 10.sub.33, 10.sub.34, 10.sub.42, 10.sub.44) corresponds to a bit having the logic state of one in the data array. When the memory cell (e.g., 10.sub.11, 10.sub.12, 10.sub.13, 10.sub.14, 10.sub.24, 10.sub.31, 10.sub.32, 10.sub.41, and 10.sub.43) corresponds to a zero in the data array, no transistor is manufactured in the memory cell.
From a point of view of management of customer's orders and production, it may be advantageous to be able to program the ROM memories as late as possible in the manufacturing process. Referring to FIG. 1b, programming the ROM 20 late in the manufacturing process can be accomplished by manufacturing the ROMs such that each memory cell 30.sub.11 . . . 30.sub.44 contains a transistor and either not connecting the transistor to the bit-line 36.sub.1 . . . 36.sub.4 and word line 38.sub.1 . . . 38.sub.4 associated with transistor's memory cell or disabling the transistor such that the transistor is made permanently non-conductive. One such method of manufacturing a transistor in every memory cell 30.sub.11 . . . 30.sub.44 and then not connecting it to the bit-lines 36.sub.1 . . . 36.sub.4 is described in U.S. Pat. No. 5,407,852 entitled "Method of Making NOR-Type ROM with LDD Cells" by Ghio et al. assigned to SGS-THOMSON Microelectronics, S.r.1., and incorporated herein by this reference.
Both of the above options are common in the manufacture of ROMs, each providing advantages and disadvantages. Since the manufacturing process can take between four and twelve weeks, programming the ROMs at the end can allow a shortening of the cycle time for the customer by having the ROMs near completion leaving only the need to program the ROM with the data. Being able to program the ROMs at the end of the manufacturing process also allows the data to be changed shortly before the ROMs are completed, permitting the customer the flexibility of changing the data array until shortly before the completion of the manufacturing process of the ROM. However, programming the ROMs at the end of the manufacturing process requires additional cost in manufacturing a transistor at every memory cell and typically can lengthen the manufacturing process, and therefore cycle time for the customer when the ROMs are not pre-prepared. This is due to additional manufacturing steps required to only connect some of the memory cells to the bit-lines and word lines or to disable the transistors so they are non-conductive.
The power consumption of the ROM is directly dependent on the number of ones in the corresponding data array. A transistor in a memory cell consumes power because of the gate capacitance and discharge of the bit-line through the transistor.
Additionally, the access time for a memory cell increases as the number of ones in the row the memory cell is in increases, and increases as the number of ones the column the memory cell increases. The worst access time is for a memory cell at the crossing of a row and column with the largest numbers of ones.
Each custom application using a ROM requires a minimum operating speed for the ROM. Typically, it is more economical to pre-prepare the ROM for the widest application and then custom program it for each individual customer application. The basic circuit must have a speed capability sufficiently fast for that of the most demanding customer part. The power consumption of most parts, including ROMs, increases as the speed increases, so the power consumption of the faster ROM is higher than the power consumption of the ROM needed for the application.
When the ROM circuits are tested, those circuits that do not meet this minimal speed requirement of the most demanding customer part cannot be used for any purpose and therefore must be discarded. This can constitute a substantial overhead expense for the manufacturer of ROM circuits. Since the economies of manufacturing are geared for one basic manufacturing process, all of the customers must receive the same basic ROM, but with customized data. Therefore, many of the customers receive parts that operate at a much higher speed and consume much more power than they require, since the custom design of parts for optimum speed and power is not economically justifiable for the manufacture of relatively low volume custom parts.